Design a variable size decoder in Verilog.

Question

RafazZ · Accepted Answer

If I understand it correctly, the question is asking about prefix code (either Huffman or Shannon-Fano). Ignore me if I understand the question incorrectly.

Assume from 1 to 3 bits are used to encode 4 codewords using Shannon-Fano encoding, and the codewords are {0, 10, 110, 111}. the decoder will have to translate the received messages into 2-bit binary codewords {00, 01, 10, 11}. A state machine will look as follows:

Reset and Start don't have to be separate states if we assume that the input is continuous and has no interruptions:
(Reset) -> (Start) -> (S0) -?> (S1) -?> (S2) -?> (S3) -> (Reset)

where -?> represents a conditional jump to either the next state or to the (Reset) state. If the conditional jump is to the (Reset) state, the output is set according to the table:
S0 ==> 00
S1 ==> 01
S2 ==> 10
S3 ==> 11 (always output this value in this state)

(-?>) means:
if (1 is received) 
  go to next state
else 
  output the appropriate value and goto (Reset)

Anonym · Answer

There's a lot of elements to typically cover in these questions, clarifications, scoping, making sure you're answering the actual question the interviewer is looking for you to answer, etc.


Could be worth doing a mock interview with one of the Prepfully Qualcomm  Digital Design Engineer experts... they've worked in the role so they clearly know how to get through the interview.


prepfully.com/practice-interviews

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